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<a href="#define-members">Macros</a> &#124;
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<div class="title">xspips_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:ga3c4c628392bc69b6295b28d8736d3c14"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga3c4c628392bc69b6295b28d8736d3c14">XSpiPs_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;XSpiPs_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:ga3c4c628392bc69b6295b28d8736d3c14"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read a register.  <a href="group__spips__v3__0.html#ga3c4c628392bc69b6295b28d8736d3c14">More...</a><br /></td></tr>
<tr class="separator:ga3c4c628392bc69b6295b28d8736d3c14"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga16d6923c47520aea34852e4c439bc02a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga16d6923c47520aea34852e4c439bc02a">XSpiPs_WriteReg</a>(BaseAddress,  RegOffset,  RegisterValue)&#160;&#160;&#160;XSpiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))</td></tr>
<tr class="memdesc:ga16d6923c47520aea34852e4c439bc02a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write to a register.  <a href="group__spips__v3__0.html#ga16d6923c47520aea34852e4c439bc02a">More...</a><br /></td></tr>
<tr class="separator:ga16d6923c47520aea34852e4c439bc02a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets from the base address of an SPI device. </p>
</div></td></tr>
<tr class="memitem:gab5bbcb1636123949d0fb41c76d7f77bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gab5bbcb1636123949d0fb41c76d7f77bd">XSPIPS_CR_OFFSET</a>&#160;&#160;&#160;0x00U</td></tr>
<tr class="memdesc:gab5bbcb1636123949d0fb41c76d7f77bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configuration.  <a href="group__spips__v3__0.html#gab5bbcb1636123949d0fb41c76d7f77bd">More...</a><br /></td></tr>
<tr class="separator:gab5bbcb1636123949d0fb41c76d7f77bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga29c45b21694c49560b05b5773a976ff5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga29c45b21694c49560b05b5773a976ff5">XSPIPS_SR_OFFSET</a>&#160;&#160;&#160;0x04U</td></tr>
<tr class="memdesc:ga29c45b21694c49560b05b5773a976ff5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status.  <a href="group__spips__v3__0.html#ga29c45b21694c49560b05b5773a976ff5">More...</a><br /></td></tr>
<tr class="separator:ga29c45b21694c49560b05b5773a976ff5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafe78a9665edf16e3114ff9c54f4b2adf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gafe78a9665edf16e3114ff9c54f4b2adf">XSPIPS_IER_OFFSET</a>&#160;&#160;&#160;0x08U</td></tr>
<tr class="memdesc:gafe78a9665edf16e3114ff9c54f4b2adf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enable.  <a href="group__spips__v3__0.html#gafe78a9665edf16e3114ff9c54f4b2adf">More...</a><br /></td></tr>
<tr class="separator:gafe78a9665edf16e3114ff9c54f4b2adf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7c019fcf06dccd6efc0026238755e9bb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga7c019fcf06dccd6efc0026238755e9bb">XSPIPS_IDR_OFFSET</a>&#160;&#160;&#160;0x0CU</td></tr>
<tr class="memdesc:ga7c019fcf06dccd6efc0026238755e9bb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Disable.  <a href="group__spips__v3__0.html#ga7c019fcf06dccd6efc0026238755e9bb">More...</a><br /></td></tr>
<tr class="separator:ga7c019fcf06dccd6efc0026238755e9bb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga809c89538cb8210bb76e00641226e3ae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga809c89538cb8210bb76e00641226e3ae">XSPIPS_IMR_OFFSET</a>&#160;&#160;&#160;0x10U</td></tr>
<tr class="memdesc:ga809c89538cb8210bb76e00641226e3ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enabled Mask.  <a href="group__spips__v3__0.html#ga809c89538cb8210bb76e00641226e3ae">More...</a><br /></td></tr>
<tr class="separator:ga809c89538cb8210bb76e00641226e3ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga96a2524f86a513015b982462f7a6ffcb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga96a2524f86a513015b982462f7a6ffcb">XSPIPS_ER_OFFSET</a>&#160;&#160;&#160;0x14U</td></tr>
<tr class="memdesc:ga96a2524f86a513015b982462f7a6ffcb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable/Disable Register.  <a href="group__spips__v3__0.html#ga96a2524f86a513015b982462f7a6ffcb">More...</a><br /></td></tr>
<tr class="separator:ga96a2524f86a513015b982462f7a6ffcb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf8f2af4e1987e431a3a4510641c475e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gaf8f2af4e1987e431a3a4510641c475e7">XSPIPS_DR_OFFSET</a>&#160;&#160;&#160;0x18U</td></tr>
<tr class="memdesc:gaf8f2af4e1987e431a3a4510641c475e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay Register.  <a href="group__spips__v3__0.html#gaf8f2af4e1987e431a3a4510641c475e7">More...</a><br /></td></tr>
<tr class="separator:gaf8f2af4e1987e431a3a4510641c475e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3720b391032e33eb4cdb6b114943abbd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga3720b391032e33eb4cdb6b114943abbd">XSPIPS_TXD_OFFSET</a>&#160;&#160;&#160;0x1CU</td></tr>
<tr class="memdesc:ga3720b391032e33eb4cdb6b114943abbd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Transmit Register.  <a href="group__spips__v3__0.html#ga3720b391032e33eb4cdb6b114943abbd">More...</a><br /></td></tr>
<tr class="separator:ga3720b391032e33eb4cdb6b114943abbd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga63d53a4c31627791748d8b77d3c24cac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga63d53a4c31627791748d8b77d3c24cac">XSPIPS_RXD_OFFSET</a>&#160;&#160;&#160;0x20U</td></tr>
<tr class="memdesc:ga63d53a4c31627791748d8b77d3c24cac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Receive Register.  <a href="group__spips__v3__0.html#ga63d53a4c31627791748d8b77d3c24cac">More...</a><br /></td></tr>
<tr class="separator:ga63d53a4c31627791748d8b77d3c24cac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4498f0a85ffc367f14d705f37a2dcc11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga4498f0a85ffc367f14d705f37a2dcc11">XSPIPS_SICR_OFFSET</a>&#160;&#160;&#160;0x24U</td></tr>
<tr class="memdesc:ga4498f0a85ffc367f14d705f37a2dcc11"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Idle Count.  <a href="group__spips__v3__0.html#ga4498f0a85ffc367f14d705f37a2dcc11">More...</a><br /></td></tr>
<tr class="separator:ga4498f0a85ffc367f14d705f37a2dcc11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga82b0c7855556fbb3d13b1d0fc3f7ae24"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga82b0c7855556fbb3d13b1d0fc3f7ae24">XSPIPS_TXWR_OFFSET</a>&#160;&#160;&#160;0x28U</td></tr>
<tr class="memdesc:ga82b0c7855556fbb3d13b1d0fc3f7ae24"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit FIFO Watermark.  <a href="group__spips__v3__0.html#ga82b0c7855556fbb3d13b1d0fc3f7ae24">More...</a><br /></td></tr>
<tr class="separator:ga82b0c7855556fbb3d13b1d0fc3f7ae24"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga708b416f4994dca83b3d50a464552286"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga708b416f4994dca83b3d50a464552286">XSPIPS_RXWR_OFFSET</a>&#160;&#160;&#160;0x2CU</td></tr>
<tr class="memdesc:ga708b416f4994dca83b3d50a464552286"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive FIFO Watermark.  <a href="group__spips__v3__0.html#ga708b416f4994dca83b3d50a464552286">More...</a><br /></td></tr>
<tr class="separator:ga708b416f4994dca83b3d50a464552286"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Configuration Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains various control bits that affects the operation of an SPI device.</p>
<p>Read/Write. </p>
</div></td></tr>
<tr class="memitem:ga8a86973f92b39e1091cdc8a1ab80dc51"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga8a86973f92b39e1091cdc8a1ab80dc51">XSPIPS_CR_MODF_GEN_EN_MASK</a>&#160;&#160;&#160;0x00020000U</td></tr>
<tr class="memdesc:ga8a86973f92b39e1091cdc8a1ab80dc51"><td class="mdescLeft">&#160;</td><td class="mdescRight">Modefail Generation Enable.  <a href="group__spips__v3__0.html#ga8a86973f92b39e1091cdc8a1ab80dc51">More...</a><br /></td></tr>
<tr class="separator:ga8a86973f92b39e1091cdc8a1ab80dc51"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab767a5fe469912c633373f607a106f7e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gab767a5fe469912c633373f607a106f7e">XSPIPS_CR_MANSTRT_MASK</a>&#160;&#160;&#160;0x00010000U</td></tr>
<tr class="memdesc:gab767a5fe469912c633373f607a106f7e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Manual Transmission Start.  <a href="group__spips__v3__0.html#gab767a5fe469912c633373f607a106f7e">More...</a><br /></td></tr>
<tr class="separator:gab767a5fe469912c633373f607a106f7e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaff958edcef4502a9c897bd5886fc63cb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gaff958edcef4502a9c897bd5886fc63cb">XSPIPS_CR_MANSTRTEN_MASK</a>&#160;&#160;&#160;0x00008000U</td></tr>
<tr class="memdesc:gaff958edcef4502a9c897bd5886fc63cb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Manual Transmission Start Enable.  <a href="group__spips__v3__0.html#gaff958edcef4502a9c897bd5886fc63cb">More...</a><br /></td></tr>
<tr class="separator:gaff958edcef4502a9c897bd5886fc63cb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga639a4d2ccc6f03518062a17c45d9ba0c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga639a4d2ccc6f03518062a17c45d9ba0c">XSPIPS_CR_SSFORCE_MASK</a>&#160;&#160;&#160;0x00004000U</td></tr>
<tr class="memdesc:ga639a4d2ccc6f03518062a17c45d9ba0c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Force Slave Select.  <a href="group__spips__v3__0.html#ga639a4d2ccc6f03518062a17c45d9ba0c">More...</a><br /></td></tr>
<tr class="separator:ga639a4d2ccc6f03518062a17c45d9ba0c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a2016ac5799028970f07ff16749e135"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga0a2016ac5799028970f07ff16749e135">XSPIPS_CR_SSCTRL_MASK</a>&#160;&#160;&#160;0x00003C00U</td></tr>
<tr class="memdesc:ga0a2016ac5799028970f07ff16749e135"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Select Decode.  <a href="group__spips__v3__0.html#ga0a2016ac5799028970f07ff16749e135">More...</a><br /></td></tr>
<tr class="separator:ga0a2016ac5799028970f07ff16749e135"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaca12200356700e8fcd67716aea4aa283"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gaca12200356700e8fcd67716aea4aa283">XSPIPS_CR_SSCTRL_SHIFT</a>&#160;&#160;&#160;10U</td></tr>
<tr class="memdesc:gaca12200356700e8fcd67716aea4aa283"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Select Decode shift.  <a href="group__spips__v3__0.html#gaca12200356700e8fcd67716aea4aa283">More...</a><br /></td></tr>
<tr class="separator:gaca12200356700e8fcd67716aea4aa283"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf018d47444763ba551c4bded4dcbdda5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gaf018d47444763ba551c4bded4dcbdda5">XSPIPS_CR_SSCTRL_MAXIMUM</a>&#160;&#160;&#160;0xFU</td></tr>
<tr class="memdesc:gaf018d47444763ba551c4bded4dcbdda5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Select maximum value.  <a href="group__spips__v3__0.html#gaf018d47444763ba551c4bded4dcbdda5">More...</a><br /></td></tr>
<tr class="separator:gaf018d47444763ba551c4bded4dcbdda5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga78439588630680bd62e34be7a0674ce3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga78439588630680bd62e34be7a0674ce3">XSPIPS_CR_SSDECEN_MASK</a>&#160;&#160;&#160;0x00000200U</td></tr>
<tr class="memdesc:ga78439588630680bd62e34be7a0674ce3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Select Decode Enable.  <a href="group__spips__v3__0.html#ga78439588630680bd62e34be7a0674ce3">More...</a><br /></td></tr>
<tr class="separator:ga78439588630680bd62e34be7a0674ce3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad2920edca049dac6e9cf45496fa5ea5a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gad2920edca049dac6e9cf45496fa5ea5a">XSPIPS_CR_PRESC_MASK</a>&#160;&#160;&#160;0x00000038U</td></tr>
<tr class="memdesc:gad2920edca049dac6e9cf45496fa5ea5a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prescaler Setting.  <a href="group__spips__v3__0.html#gad2920edca049dac6e9cf45496fa5ea5a">More...</a><br /></td></tr>
<tr class="separator:gad2920edca049dac6e9cf45496fa5ea5a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga89ff9aa9c710a64a2ea00031fa3e38e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga89ff9aa9c710a64a2ea00031fa3e38e5">XSPIPS_CR_PRESC_SHIFT</a>&#160;&#160;&#160;3U</td></tr>
<tr class="memdesc:ga89ff9aa9c710a64a2ea00031fa3e38e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prescaler shift.  <a href="group__spips__v3__0.html#ga89ff9aa9c710a64a2ea00031fa3e38e5">More...</a><br /></td></tr>
<tr class="separator:ga89ff9aa9c710a64a2ea00031fa3e38e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5c36cba75a4a522d258ad5cd668d39da"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga5c36cba75a4a522d258ad5cd668d39da">XSPIPS_CR_PRESC_MAXIMUM</a>&#160;&#160;&#160;0x07U</td></tr>
<tr class="memdesc:ga5c36cba75a4a522d258ad5cd668d39da"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prescaler maximum value.  <a href="group__spips__v3__0.html#ga5c36cba75a4a522d258ad5cd668d39da">More...</a><br /></td></tr>
<tr class="separator:ga5c36cba75a4a522d258ad5cd668d39da"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4a6535d62a7cad8209d615146f5f050c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga4a6535d62a7cad8209d615146f5f050c">XSPIPS_CR_CPHA_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga4a6535d62a7cad8209d615146f5f050c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Phase Configuration.  <a href="group__spips__v3__0.html#ga4a6535d62a7cad8209d615146f5f050c">More...</a><br /></td></tr>
<tr class="separator:ga4a6535d62a7cad8209d615146f5f050c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad085464580e29731d0eafc1b6eb4bdb0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gad085464580e29731d0eafc1b6eb4bdb0">XSPIPS_CR_CPOL_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:gad085464580e29731d0eafc1b6eb4bdb0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Polarity Configuration.  <a href="group__spips__v3__0.html#gad085464580e29731d0eafc1b6eb4bdb0">More...</a><br /></td></tr>
<tr class="separator:gad085464580e29731d0eafc1b6eb4bdb0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga134064afeaf8e1a72b0f927d6686794f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga134064afeaf8e1a72b0f927d6686794f">XSPIPS_CR_MSTREN_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga134064afeaf8e1a72b0f927d6686794f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Mode Enable.  <a href="group__spips__v3__0.html#ga134064afeaf8e1a72b0f927d6686794f">More...</a><br /></td></tr>
<tr class="separator:ga134064afeaf8e1a72b0f927d6686794f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaec8a40193324debd139e5f47fbb2c943"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gaec8a40193324debd139e5f47fbb2c943">XSPIPS_CR_RESET_STATE</a>&#160;&#160;&#160;0x00020000U</td></tr>
<tr class="memdesc:gaec8a40193324debd139e5f47fbb2c943"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode Fail Generation Enable.  <a href="group__spips__v3__0.html#gaec8a40193324debd139e5f47fbb2c943">More...</a><br /></td></tr>
<tr class="separator:gaec8a40193324debd139e5f47fbb2c943"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">SPI Interrupt Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p><b>SPI Status Register</b></p>
<p>This register holds the interrupt status flags for an SPI device. Some of the flags are level triggered, which means that they are set as long as the interrupt condition exists. Other flags are edge triggered, which means they are set once the interrupt condition occurs and remain set until they are cleared by software. The interrupts are cleared by writing a '1' to the interrupt bit position in the Status Register. Read/Write.</p>
<p><b>SPI Interrupt Enable Register</b></p>
<p>This register is used to enable chosen interrupts for an SPI device. Writing a '1' to a bit in this register sets the corresponding bit in the SPI Interrupt Mask register. Write only.</p>
<p><b>SPI Interrupt Disable Register </b></p>
<p>This register is used to disable chosen interrupts for an SPI device. Writing a '1' to a bit in this register clears the corresponding bit in the SPI Interrupt Mask register. Write only.</p>
<p><b>SPI Interrupt Mask Register</b></p>
<p>This register shows the enabled/disabled interrupts of an SPI device. Read only.</p>
<p>All four registers have the same bit definitions. They are only defined once for each of the Interrupt Enable Register, Interrupt Disable Register, Interrupt Mask Register, and Channel Interrupt Status Register </p>
</div></td></tr>
<tr class="memitem:ga7e7034f3e256ec752fe7cdef9b090ff6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga7e7034f3e256ec752fe7cdef9b090ff6">XSPIPS_IXR_TXUF_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga7e7034f3e256ec752fe7cdef9b090ff6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx FIFO Underflow.  <a href="group__spips__v3__0.html#ga7e7034f3e256ec752fe7cdef9b090ff6">More...</a><br /></td></tr>
<tr class="separator:ga7e7034f3e256ec752fe7cdef9b090ff6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9fc7edf6f528d10a32f847f7cb6177cd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga9fc7edf6f528d10a32f847f7cb6177cd">XSPIPS_IXR_RXFULL_MASK</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga9fc7edf6f528d10a32f847f7cb6177cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx FIFO Full.  <a href="group__spips__v3__0.html#ga9fc7edf6f528d10a32f847f7cb6177cd">More...</a><br /></td></tr>
<tr class="separator:ga9fc7edf6f528d10a32f847f7cb6177cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga72359f1b9dc7e5c5f0c5fdb3f6d62fc4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga72359f1b9dc7e5c5f0c5fdb3f6d62fc4">XSPIPS_IXR_RXNEMPTY_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga72359f1b9dc7e5c5f0c5fdb3f6d62fc4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx FIFO Not Empty.  <a href="group__spips__v3__0.html#ga72359f1b9dc7e5c5f0c5fdb3f6d62fc4">More...</a><br /></td></tr>
<tr class="separator:ga72359f1b9dc7e5c5f0c5fdb3f6d62fc4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8553285ef54073a9aa160bbd2035ce2e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga8553285ef54073a9aa160bbd2035ce2e">XSPIPS_IXR_TXFULL_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga8553285ef54073a9aa160bbd2035ce2e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx FIFO Full.  <a href="group__spips__v3__0.html#ga8553285ef54073a9aa160bbd2035ce2e">More...</a><br /></td></tr>
<tr class="separator:ga8553285ef54073a9aa160bbd2035ce2e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad8525498172f10882b4a7cf59c660577"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gad8525498172f10882b4a7cf59c660577">XSPIPS_IXR_TXOW_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gad8525498172f10882b4a7cf59c660577"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx FIFO Overwater.  <a href="group__spips__v3__0.html#gad8525498172f10882b4a7cf59c660577">More...</a><br /></td></tr>
<tr class="separator:gad8525498172f10882b4a7cf59c660577"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1f3e107983ccd2aa609a61691a4acbd5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga1f3e107983ccd2aa609a61691a4acbd5">XSPIPS_IXR_MODF_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga1f3e107983ccd2aa609a61691a4acbd5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode Fault.  <a href="group__spips__v3__0.html#ga1f3e107983ccd2aa609a61691a4acbd5">More...</a><br /></td></tr>
<tr class="separator:ga1f3e107983ccd2aa609a61691a4acbd5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga04768ee339e209d5134491b7dc5291f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga04768ee339e209d5134491b7dc5291f7">XSPIPS_IXR_RXOVR_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga04768ee339e209d5134491b7dc5291f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx FIFO Overrun.  <a href="group__spips__v3__0.html#ga04768ee339e209d5134491b7dc5291f7">More...</a><br /></td></tr>
<tr class="separator:ga04768ee339e209d5134491b7dc5291f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8ecb6f78f0e0f71ac85462071015353d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga8ecb6f78f0e0f71ac85462071015353d">XSPIPS_IXR_DFLT_MASK</a>&#160;&#160;&#160;0x00000027U</td></tr>
<tr class="memdesc:ga8ecb6f78f0e0f71ac85462071015353d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Default interrupts mask.  <a href="group__spips__v3__0.html#ga8ecb6f78f0e0f71ac85462071015353d">More...</a><br /></td></tr>
<tr class="separator:ga8ecb6f78f0e0f71ac85462071015353d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaefc16123501616910c471781dc5a6763"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gaefc16123501616910c471781dc5a6763">XSPIPS_IXR_WR_TO_CLR_MASK</a>&#160;&#160;&#160;0x00000043U</td></tr>
<tr class="memdesc:gaefc16123501616910c471781dc5a6763"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupts which need write to clear.  <a href="group__spips__v3__0.html#gaefc16123501616910c471781dc5a6763">More...</a><br /></td></tr>
<tr class="separator:gaefc16123501616910c471781dc5a6763"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad01d887bc3e3b00c6a25ed26b3f71c4a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gad01d887bc3e3b00c6a25ed26b3f71c4a">XSPIPS_ISR_RESET_STATE</a>&#160;&#160;&#160;0x04U</td></tr>
<tr class="memdesc:gad01d887bc3e3b00c6a25ed26b3f71c4a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Default to tx/rx reg empty.  <a href="group__spips__v3__0.html#gad01d887bc3e3b00c6a25ed26b3f71c4a">More...</a><br /></td></tr>
<tr class="separator:gad01d887bc3e3b00c6a25ed26b3f71c4a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga58051be9e1582d618f4c75be29a32734"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga58051be9e1582d618f4c75be29a32734">XSPIPS_IXR_DISABLE_ALL_MASK</a>&#160;&#160;&#160;0x00000043U</td></tr>
<tr class="memdesc:ga58051be9e1582d618f4c75be29a32734"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable all interrupts.  <a href="group__spips__v3__0.html#ga58051be9e1582d618f4c75be29a32734">More...</a><br /></td></tr>
<tr class="separator:ga58051be9e1582d618f4c75be29a32734"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Enable Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used to enable or disable an SPI device.</p>
<p>Read/Write </p>
</div></td></tr>
<tr class="memitem:gaa31de4b8fd2bc4cd055be77a535f9048"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gaa31de4b8fd2bc4cd055be77a535f9048">XSPIPS_ER_ENABLE_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gaa31de4b8fd2bc4cd055be77a535f9048"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPI Enable Bit Mask.  <a href="group__spips__v3__0.html#gaa31de4b8fd2bc4cd055be77a535f9048">More...</a><br /></td></tr>
<tr class="separator:gaa31de4b8fd2bc4cd055be77a535f9048"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Delay Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used to program timing delays in slave mode.</p>
<p>Read/Write </p>
</div></td></tr>
<tr class="memitem:ga2cfead0ca3e714dae4cd98538575e723"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga2cfead0ca3e714dae4cd98538575e723">XSPIPS_DR_NSS_MASK</a>&#160;&#160;&#160;0xFF000000U</td></tr>
<tr class="memdesc:ga2cfead0ca3e714dae4cd98538575e723"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay for slave select de-assertion between word transfers mask.  <a href="group__spips__v3__0.html#ga2cfead0ca3e714dae4cd98538575e723">More...</a><br /></td></tr>
<tr class="separator:ga2cfead0ca3e714dae4cd98538575e723"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2d56d5e1023b1e2f11b67d0cfc4dac3e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga2d56d5e1023b1e2f11b67d0cfc4dac3e">XSPIPS_DR_NSS_SHIFT</a>&#160;&#160;&#160;24U</td></tr>
<tr class="memdesc:ga2d56d5e1023b1e2f11b67d0cfc4dac3e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay for slave select de-assertion between word transfers shift.  <a href="group__spips__v3__0.html#ga2d56d5e1023b1e2f11b67d0cfc4dac3e">More...</a><br /></td></tr>
<tr class="separator:ga2d56d5e1023b1e2f11b67d0cfc4dac3e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad21ad068d7d43fe94abb40c5d40a1bd0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gad21ad068d7d43fe94abb40c5d40a1bd0">XSPIPS_DR_BTWN_MASK</a>&#160;&#160;&#160;0x00FF0000U</td></tr>
<tr class="memdesc:gad21ad068d7d43fe94abb40c5d40a1bd0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay Between Transfers mask.  <a href="group__spips__v3__0.html#gad21ad068d7d43fe94abb40c5d40a1bd0">More...</a><br /></td></tr>
<tr class="separator:gad21ad068d7d43fe94abb40c5d40a1bd0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8ff0e7a46a2566b4558a3a5f39819591"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga8ff0e7a46a2566b4558a3a5f39819591">XSPIPS_DR_BTWN_SHIFT</a>&#160;&#160;&#160;16U</td></tr>
<tr class="memdesc:ga8ff0e7a46a2566b4558a3a5f39819591"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay Between Transfers shift.  <a href="group__spips__v3__0.html#ga8ff0e7a46a2566b4558a3a5f39819591">More...</a><br /></td></tr>
<tr class="separator:ga8ff0e7a46a2566b4558a3a5f39819591"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4a6fad4316227a5337c49e2af28ee8ef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga4a6fad4316227a5337c49e2af28ee8ef">XSPIPS_DR_AFTER_MASK</a>&#160;&#160;&#160;0x0000FF00U</td></tr>
<tr class="memdesc:ga4a6fad4316227a5337c49e2af28ee8ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay After Transfers mask.  <a href="group__spips__v3__0.html#ga4a6fad4316227a5337c49e2af28ee8ef">More...</a><br /></td></tr>
<tr class="separator:ga4a6fad4316227a5337c49e2af28ee8ef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga56b1f2b236db35a9be0c75eb8bedb289"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga56b1f2b236db35a9be0c75eb8bedb289">XSPIPS_DR_AFTER_SHIFT</a>&#160;&#160;&#160;8U</td></tr>
<tr class="memdesc:ga56b1f2b236db35a9be0c75eb8bedb289"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay After Transfers shift.  <a href="group__spips__v3__0.html#ga56b1f2b236db35a9be0c75eb8bedb289">More...</a><br /></td></tr>
<tr class="separator:ga56b1f2b236db35a9be0c75eb8bedb289"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1c61ee31777ca9fc61bb50dd86d45598"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga1c61ee31777ca9fc61bb50dd86d45598">XSPIPS_DR_INIT_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga1c61ee31777ca9fc61bb50dd86d45598"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay Initially mask.  <a href="group__spips__v3__0.html#ga1c61ee31777ca9fc61bb50dd86d45598">More...</a><br /></td></tr>
<tr class="separator:ga1c61ee31777ca9fc61bb50dd86d45598"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Slave Idle Count Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register defines the number of pclk cycles the slave waits for a the SPI clock to become stable in quiescent state before it can detect the start of the next transfer in CPHA = 1 mode.</p>
<p>Read/Write </p>
</div></td></tr>
<tr class="memitem:gae6d909341b39d857ea6e955e076e9024"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gae6d909341b39d857ea6e955e076e9024">XSPIPS_SICR_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:gae6d909341b39d857ea6e955e076e9024"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Idle Count Mask.  <a href="group__spips__v3__0.html#gae6d909341b39d857ea6e955e076e9024">More...</a><br /></td></tr>
<tr class="separator:gae6d909341b39d857ea6e955e076e9024"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Transmit FIFO Watermark Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register defines the watermark setting for the Transmit FIFO.</p>
<p>The transmit FIFO is 128 bytes deep, so the register is 7 bits. Valid values are 1 to 128. </p>
</div></td></tr>
<tr class="memitem:gac3beb6059f26dbf07ad7f2e8f1b8449c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gac3beb6059f26dbf07ad7f2e8f1b8449c">XSPIPS_TXWR_MASK</a>&#160;&#160;&#160;0x0000007FU</td></tr>
<tr class="memdesc:gac3beb6059f26dbf07ad7f2e8f1b8449c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit Watermark Mask.  <a href="group__spips__v3__0.html#gac3beb6059f26dbf07ad7f2e8f1b8449c">More...</a><br /></td></tr>
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<tr class="memitem:ga7a9a7acd83ec76540bc267398ee3bb20"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga7a9a7acd83ec76540bc267398ee3bb20">XSPIPS_TXWR_RESET_VALUE</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga7a9a7acd83ec76540bc267398ee3bb20"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit Watermark register reset value.  <a href="group__spips__v3__0.html#ga7a9a7acd83ec76540bc267398ee3bb20">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Receive FIFO Watermark Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register defines the watermark setting for the Receive FIFO.</p>
<p>The receive FIFO is 128 bytes deep, so the register is 7 bits. Valid values are 1 to 128. </p>
</div></td></tr>
<tr class="memitem:ga8e6d59478b0789f6ea58abbc85fc1947"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#ga8e6d59478b0789f6ea58abbc85fc1947">XSPIPS_RXWR_MASK</a>&#160;&#160;&#160;0x0000007FU</td></tr>
<tr class="memdesc:ga8e6d59478b0789f6ea58abbc85fc1947"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive Watermark Mask.  <a href="group__spips__v3__0.html#ga8e6d59478b0789f6ea58abbc85fc1947">More...</a><br /></td></tr>
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<tr class="memitem:gab806ad4fc5536152742b74aa67f91cc7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gab806ad4fc5536152742b74aa67f91cc7">XSPIPS_RXWR_RESET_VALUE</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gab806ad4fc5536152742b74aa67f91cc7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive Watermark register reset value.  <a href="group__spips__v3__0.html#gab806ad4fc5536152742b74aa67f91cc7">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">FIFO Depth</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This macro provides the depth of transmit FIFO and receive FIFO. </p>
</div></td></tr>
<tr class="memitem:gad82a11ae1f014d578834f1522a8a94ca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gad82a11ae1f014d578834f1522a8a94ca">XSPIPS_FIFO_DEPTH</a>&#160;&#160;&#160;128U</td></tr>
<tr class="memdesc:gad82a11ae1f014d578834f1522a8a94ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO depth of Tx and Rx.  <a href="group__spips__v3__0.html#gad82a11ae1f014d578834f1522a8a94ca">More...</a><br /></td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:gab466a4718bbee60293dc226ca043d5b5"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__spips__v3__0.html#gab466a4718bbee60293dc226ca043d5b5">XSpiPs_ResetHw</a> (u32 BaseAddress)</td></tr>
<tr class="memdesc:gab466a4718bbee60293dc226ca043d5b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Resets the spi module.  <a href="group__spips__v3__0.html#gab466a4718bbee60293dc226ca043d5b5">More...</a><br /></td></tr>
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